The GSBarnDoor project, also called just "Barn Door" or "IIgs Barn Door", was a collaborative project between James Littlejohn of 8bitsystem.com and Henry of ReActiveMicro. Henrys' involvement started in May of 2011.
The GSBarnDoor was to be a kind of CPU Replace Board for the IIgs, and allow 32bit processing.
Project Status: Unknown. Assumed abandoned by 8bitsystem.com.
Henry from ReActiveMicro was contacted and asked if he would like to help with certain parts of the project since he had contacts at VLSI Concepts. Henry would also be in charge of PCB layout and design, selecting the components for the project, assembly, and Alpha stage testing. Once the design was able to be tested in a IIe, Henrys' work would be complete. James Littlejohn would then take over and continue with the final testing and ultimately his GSBarnDoor project.
Henry chose VLSI Concepts as they could provide a licensed, working core based on their existing designs. Henry and the owner of VLSI Concepts would work together to provide a working CPU replacement based in an FPGA. James Littlejohn and could then use the CPU replacement design as a bases for the GSBarnDoor project.
The core that VLSI Concepts provided did 8bit, 16bit, and also allowed for 32bit processing based on the WDC 832 CPU datasheet. They completed their IP core around November 2011, and it has been available since then for license from their site.
Henry completed a proto layout and ordered PCBs on April 25th, 2011. When they arrived he assembled and produced a mostly "working" Alpha unit. The unit was then sent to James Littlejohn to document all found issues. He would then work directly with VLSI Concepts to revolve the design in to a fully functional core for his projects' needs.
When Henry left the project the design still needed several areas addressed, such as timing. When installed and tested in a IIe for example, the IIe would lockup. The design also needed all OP codes to be fully tested, cycles measured and counted, and all timings confirmed. All aspects of the IP core needed to be confirmed to the agreed datasheet. This part of the project was never completed.