User:Xjmaas - Revision history

Xjmaas: /* Current Issues */

2019-07-05T09:39:21Z

Current Issues

← Older revision		Revision as of 02:39, 5 July 2019
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	File:Ref n ROM CE.png\|Reference n_ROM_CE		File:Ref n ROM CE.png\|Reference n_ROM_CE
	File:Ref n ROM OE.png\|Reference n_ROM_OE		File:Ref n ROM OE.png\|Reference n_ROM_OE
	File:Ref n CFFF.png\|Reference n_CFFF (ignore unconnected pin)		File:Ref n CFFF.png\|Reference n_CFFF <br />(ignore unconnected pin)
	File:Ref PHI2.png\|Reference for PHI2 clock regeneration		File:Ref PHI2.png\|Reference for PHI2 clock regeneration
	</gallery>		</gallery>

Xjmaas: /* Current Issues */

2019-07-05T09:36:43Z

Current Issues

← Older revision		Revision as of 02:36, 5 July 2019
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	File:Ref n ROM CE.png\|Reference n_ROM_CE		File:Ref n ROM CE.png\|Reference n_ROM_CE
	File:Ref n ROM OE.png\|Reference n_ROM_OE		File:Ref n ROM OE.png\|Reference n_ROM_OE
	File:Ref n CFFF.png\|Reference n_CFFF		File:Ref n CFFF.png\|Reference n_CFFF (ignore unconnected pin)
	File:Ref PHI2.png\|Reference for PHI2 clock regeneration		File:Ref PHI2.png\|Reference for PHI2 clock regeneration
	</gallery>		</gallery>

Xjmaas: /* Current Issues */

2019-07-03T09:55:48Z

Current Issues

← Older revision		Revision as of 02:55, 3 July 2019
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	==== Current Issues ====		==== Current Issues ====
	* In ~~order~~ to ~~read from~~ the EEPROM, I have to ~~use~~ some ~~slot signals to enable~~ the ~~EEPROM when the slot is accessed~~, in ~~either the SLOTROM~~ (<~~code~~>~~$Cx00-$CxFF, x = 1~~..~~7</code>) or AUXROM (<code>$C800-$~~CFFF</~~code~~>~~). Accessing $CFFF should disable the AUXROM. This has to be done in the CPLD, which also handles the generation of the PHI2 signal and will contain the SPI controller~~		* In an effort to minimize the count of components, I opted to include the chip select logic for the EEPROM into CPLD, there should be some room left. For this I have to develop some simple (sub)entities for the VHDL project. I didn't get it right for now, but I have included some reference designs (made in Kicad). These still have to be (re)written in VHDL
			<gallery class="center" widths=160px heights=60px>
			File:Ref n ROM CE.png\|Reference n_ROM_CE
			File:Ref n ROM OE.png\|Reference n_ROM_OE
			File:Ref n CFFF.png\|Reference n_CFFF
			File:Ref PHI2.png\|Reference for PHI2 clock regeneration
			</gallery>

	==== File(s) ====		==== File(s) ====

Xjmaas: /* Current Issues */

2019-07-03T07:42:50Z

Current Issues

← Older revision		Revision as of 00:42, 3 July 2019
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	==== Current Issues ====		==== Current Issues ====
	~~: The biggest issue~~ I ~~still encounter is that I can't get~~ the ~~basic control signals from~~ the slot ~~put into~~ the ~~correct VHDL~~ code ~~in my CPLD project~~. ~~These signals I have to process are e~~.g. ~~/IOSEL~~, ~~/DEVSEL~~ and ~~/IOSTROBE.~~		* In order to read from the EEPROM, I have to use some slot signals to enable the EEPROM when the slot is accessed, in either the SLOTROM (<code>$Cx00-$CxFF, x = 1..7</code>) or AUXROM (<code>$C800-$CFFF</code>). Accessing $CFFF should disable the AUXROM. This has to be done in the CPLD, which also handles the generation of the PHI2 signal and will contain the SPI controller
	:I will ~~try to add~~ the ~~schematic representation to this page when I have it recreated.~~
	==== File(s) ====		==== File(s) ====
	: [[Media:A2 SD 3.3V.zip\|Kicad Project]]		: [[Media:A2 SD 3.3V.zip\|Kicad Project]]

Xjmaas: /* Description */

2019-07-03T07:18:03Z

Description

← Older revision		Revision as of 00:18, 3 July 2019
Line 26:		Line 26:
	: active		: active
	==== Description ====		==== Description ====
	: Board - Preliminary board design is done and a few bare boards have been ordered. CPLD implementation is incomplete, I still lack some knowledge of VHDL to get some basic signals to work. The CPLD I use, is the Xilinx XC9572XL, as that is a 3.3V CPLD, but with 5V tolerant inputs.<br />		* '''Board''' - Preliminary board design is done and a few bare boards have been ordered.
	:ROM - A basic ROM has been had working with a breadboard like environment.<br /><br />My goal is to create an expansion card which uses the Multi Media Card SPI interface, based on the [http://6502.org/users/andre/spi65b/index.html SPI65/B by André Fachat]<br />(which in turn is a VHDL reimplementation of [http://sbc.rictor.org/65spi.html Daryl Rictor's 65SPI]) as a (raw) mass storage device.		* '''CPLD''' - CPLD implementation is incomplete, I still lack some knowledge of VHDL to get some basic signals to work. The CPLD I use, is the Xilinx XC9572XL, as that is a 3.3V CPLD, but with 5V tolerant inputs.<br />
			* '''ROM''' - A basic ROM has been had working with a breadboard like environment.<br /><br />My goal is to create an expansion card which uses the Multi Media Card SPI interface, based on the [http://6502.org/users/andre/spi65b/index.html SPI65/B by André Fachat]<br />(which in turn is a VHDL reimplementation of [http://sbc.rictor.org/65spi.html Daryl Rictor's 65SPI]) as a (raw) mass storage device.

	==== Current Issues ====		==== Current Issues ====
	: The biggest issue I still encounter is that I can't get the basic control signals from the slot put into the correct VHDL code in my CPLD project. These signals I have to process are e.g. /IOSEL, /DEVSEL and /IOSTROBE.		: The biggest issue I still encounter is that I can't get the basic control signals from the slot put into the correct VHDL code in my CPLD project. These signals I have to process are e.g. /IOSEL, /DEVSEL and /IOSTROBE.

Xjmaas: /* Apple ][ Multi Media Card (MMC) Mass Storage card */

2019-07-02T05:48:01Z

Apple ][ Multi Media Card (MMC) Mass Storage card

← Older revision		Revision as of 22:48, 1 July 2019
Line 28:		Line 28:
	: Board - Preliminary board design is done and a few bare boards have been ordered. CPLD implementation is incomplete, I still lack some knowledge of VHDL to get some basic signals to work. The CPLD I use, is the Xilinx XC9572XL, as that is a 3.3V CPLD, but with 5V tolerant inputs.<br />		: Board - Preliminary board design is done and a few bare boards have been ordered. CPLD implementation is incomplete, I still lack some knowledge of VHDL to get some basic signals to work. The CPLD I use, is the Xilinx XC9572XL, as that is a 3.3V CPLD, but with 5V tolerant inputs.<br />
	:ROM - A basic ROM has been had working with a breadboard like environment.<br /><br />My goal is to create an expansion card which uses the Multi Media Card SPI interface, based on the [http://6502.org/users/andre/spi65b/index.html SPI65/B by André Fachat]<br />(which in turn is a VHDL reimplementation of [http://sbc.rictor.org/65spi.html Daryl Rictor's 65SPI]) as a (raw) mass storage device.		:ROM - A basic ROM has been had working with a breadboard like environment.<br /><br />My goal is to create an expansion card which uses the Multi Media Card SPI interface, based on the [http://6502.org/users/andre/spi65b/index.html SPI65/B by André Fachat]<br />(which in turn is a VHDL reimplementation of [http://sbc.rictor.org/65spi.html Daryl Rictor's 65SPI]) as a (raw) mass storage device.
			==== Current Issues ====
			: The biggest issue I still encounter is that I can't get the basic control signals from the slot put into the correct VHDL code in my CPLD project. These signals I have to process are e.g. /IOSEL, /DEVSEL and /IOSTROBE.
			:I will try to add the schematic representation to this page when I have it recreated.
	==== File(s) ====		==== File(s) ====
	: [[Media:A2 SD 3.3V.zip\|Kicad Project]]		: [[Media:A2 SD 3.3V.zip\|Kicad Project]]

Xjmaas at 05:41, 2 July 2019

2019-07-02T05:41:21Z

← Older revision		Revision as of 22:41, 1 July 2019
Line 29:		Line 29:
	:ROM - A basic ROM has been had working with a breadboard like environment.<br /><br />My goal is to create an expansion card which uses the Multi Media Card SPI interface, based on the [http://6502.org/users/andre/spi65b/index.html SPI65/B by André Fachat]<br />(which in turn is a VHDL reimplementation of [http://sbc.rictor.org/65spi.html Daryl Rictor's 65SPI]) as a (raw) mass storage device.		:ROM - A basic ROM has been had working with a breadboard like environment.<br /><br />My goal is to create an expansion card which uses the Multi Media Card SPI interface, based on the [http://6502.org/users/andre/spi65b/index.html SPI65/B by André Fachat]<br />(which in turn is a VHDL reimplementation of [http://sbc.rictor.org/65spi.html Daryl Rictor's 65SPI]) as a (raw) mass storage device.
	==== File(s) ====		==== File(s) ====
	: [[~~File~~:A2 SD 3.3V.zip \| Kicad Project]]		: [[Media:A2 SD 3.3V.zip\|Kicad Project]]
	: [[~~File~~:A2 SD.zip \| Xilinx ISE 14.7 Project]]		: [[Media:A2 SD.zip\|Xilinx ISE 14.7 Project]]

	=== Apple Plotter pens replica ===		=== Apple Plotter pens replica ===

Xjmaas: /* Apple ][ Slot connector symbol and footprints I designed for */

2019-07-02T05:37:19Z

Apple ][ Slot connector symbol and footprints I designed for

← Older revision		Revision as of 22:37, 1 July 2019
Line 10:		Line 10:
	The Apple II is a renewed hobby of mine and I have set my self to the following projects		The Apple II is a renewed hobby of mine and I have set my self to the following projects

	=== Apple ][ Slot connector symbol and footprints I designed for ===		=== Apple ][ Slot connector symbol and footprints I designed for Kicad and Eagle===

	==== Status ====		==== Status ====
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	: [http://www.xjmaas.nl/wp-content/uploads/2016/04/Apple2_bus.zip kicad]		: [http://www.xjmaas.nl/wp-content/uploads/2016/04/Apple2_bus.zip kicad]
	: [http://www.xjmaas.nl/wp-content/uploads/2016/04/con-apple2.lbr_.zip Eagle]		: [http://www.xjmaas.nl/wp-content/uploads/2016/04/con-apple2.lbr_.zip Eagle]


	=== Apple ][ Multi Media Card (MMC) Mass Storage card ===		=== Apple ][ Multi Media Card (MMC) Mass Storage card ===

Xjmaas: Added the Xilinx ISE 14.7 project for the A2 SD/MMC Project

2019-07-02T05:35:54Z

Added the Xilinx ISE 14.7 project for the A2 SD/MMC Project

← Older revision		Revision as of 22:35, 1 July 2019
Line 30:		Line 30:
	:ROM - A basic ROM has been had working with a breadboard like environment.<br /><br />My goal is to create an expansion card which uses the Multi Media Card SPI interface, based on the [http://6502.org/users/andre/spi65b/index.html SPI65/B by André Fachat]<br />(which in turn is a VHDL reimplementation of [http://sbc.rictor.org/65spi.html Daryl Rictor's 65SPI]) as a (raw) mass storage device.		:ROM - A basic ROM has been had working with a breadboard like environment.<br /><br />My goal is to create an expansion card which uses the Multi Media Card SPI interface, based on the [http://6502.org/users/andre/spi65b/index.html SPI65/B by André Fachat]<br />(which in turn is a VHDL reimplementation of [http://sbc.rictor.org/65spi.html Daryl Rictor's 65SPI]) as a (raw) mass storage device.
	==== File(s) ====		==== File(s) ====
	: [[File:A2 SD 3.3V.zip\|Kicad Project]]		: [[File:A2 SD 3.3V.zip \| Kicad Project]]
	: [[File:A2 SD.zip\|Xilinx ISE 14.7 Project]]		: [[File:A2 SD.zip \| Xilinx ISE 14.7 Project]]

	=== Apple Plotter pens replica ===		=== Apple Plotter pens replica ===

Xjmaas at 05:34, 2 July 2019

2019-07-02T05:34:34Z

← Older revision		Revision as of 22:34, 1 July 2019
Line 27:		Line 27:
	: active		: active
	==== Description ====		==== Description ====
	: Board - Preliminary board design is done and a few bare boards have been ordered. CPLD implementation is incomplete, I still lack some knowledge of VHDL to get some basic signals to work.<br />ROM - A basic ROM has been had working with a breadboard like environment<br /><br />My goal is to create an expansion card which uses the Multi Media Card SPI interface, based on the [http://6502.org/users/andre/spi65b/index.html SPI65/B by André Fachat]<br />(which in turn is a VHDL reimplementation of [http://sbc.rictor.org/65spi.html Daryl Rictor's 65SPI]) as a (raw) mass storage device.		: Board - Preliminary board design is done and a few bare boards have been ordered. CPLD implementation is incomplete, I still lack some knowledge of VHDL to get some basic signals to work. The CPLD I use, is the Xilinx XC9572XL, as that is a 3.3V CPLD, but with 5V tolerant inputs.<br />
			:ROM - A basic ROM has been had working with a breadboard like environment.<br /><br />My goal is to create an expansion card which uses the Multi Media Card SPI interface, based on the [http://6502.org/users/andre/spi65b/index.html SPI65/B by André Fachat]<br />(which in turn is a VHDL reimplementation of [http://sbc.rictor.org/65spi.html Daryl Rictor's 65SPI]) as a (raw) mass storage device.
	==== File(s) ====		==== File(s) ====
	: [[File:A2 SD 3.3V.zip\|Kicad Project]]		: [[File:A2 SD 3.3V.zip\|Kicad Project]]
			: [[File:A2 SD.zip\|Xilinx ISE 14.7 Project]]

	=== Apple Plotter pens replica ===		=== Apple Plotter pens replica ===
Line 35:		Line 37:
	: On hold		: On hold
	==== Description ====		==== Description ====
	: At the moment this project has halted as I am trying to understand how to make "shell-like" models/objects this small using the 3D-printers we have at our school		: At the moment this project has halted as I am trying to understand how to make "shell-like" models/objects this small using the 3D-printers we have at our school.

← Older revision		Revision as of 02:39, 5 July 2019
Line 35:		Line 35:
	File:Ref n ROM CE.png\|Reference n_ROM_CE		File:Ref n ROM CE.png\|Reference n_ROM_CE
	File:Ref n ROM OE.png\|Reference n_ROM_OE		File:Ref n ROM OE.png\|Reference n_ROM_OE
	File:Ref n CFFF.png\|Reference n_CFFF (ignore unconnected pin)		File:Ref n CFFF.png\|Reference n_CFFF <br />(ignore unconnected pin)
	File:Ref PHI2.png\|Reference for PHI2 clock regeneration		File:Ref PHI2.png\|Reference for PHI2 clock regeneration
	</gallery>		</gallery>

← Older revision		Revision as of 02:36, 5 July 2019
Line 35:		Line 35:
	File:Ref n ROM CE.png\|Reference n_ROM_CE		File:Ref n ROM CE.png\|Reference n_ROM_CE
	File:Ref n ROM OE.png\|Reference n_ROM_OE		File:Ref n ROM OE.png\|Reference n_ROM_OE
	File:Ref n CFFF.png\|Reference n_CFFF		File:Ref n CFFF.png\|Reference n_CFFF (ignore unconnected pin)
	File:Ref PHI2.png\|Reference for PHI2 clock regeneration		File:Ref PHI2.png\|Reference for PHI2 clock regeneration
	</gallery>		</gallery>