UltraWarp - Revision history

Cryu: Document speed issue with Dan ][ ethernet

2023-10-18T05:21:41Z

Document speed issue with Dan ][ ethernet

← Older revision		Revision as of 22:21, 17 October 2023
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	\| No issues encountered.		\| No issues encountered.

			\|-
			\| Dan ][ SD Controller
			\| Apple IIe<br />UltraWarp 1.91RM 16MHz
			\| Yes
			\| Yes
			\| If using the Wiznet ethernet daughterboard with ADTPro, the slot speed must be set to SLOW.
	\|}		\|}

Cryu: Make the ADTPro crash analysis more accurate

2023-10-18T05:08:50Z

Make the ADTPro crash analysis more accurate

← Older revision		Revision as of 22:08, 17 October 2023
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	=== ADTPro ===		=== ADTPro ===
	ADTPro-2.1.0 attempts to unilaterally disable the ZipChip and TransWarp accelerators during a critical timing loop. Unfortunately, that causes the ~~UltraWarp~~ to ~~corrupt the screen~~.		ADTPro-2.1.0 attempts to unilaterally disable the ZipChip and TransWarp accelerators during a critical timing loop. Unfortunately, the ZipChip is enabled by a write to $C05B, which is the same memory location that disables the UltraWarp ... which causes the machine to crash.

	Replacing the offending instructions with instructions appropriate for the UltraWarp solves the problem.		Replacing the offending instructions with instructions appropriate for the UltraWarp solves the problem.

Cryu: Document ADTPro issue, add link to patched client

2023-10-18T04:57:31Z

Document ADTPro issue, add link to patched client

← Older revision		Revision as of 21:57, 17 October 2023
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	=== No-Slot Clock ===		=== No-Slot Clock ===
	The WDC 65C16S has a timing incompatibility with the [[No-Slot Clock]] and must use a modified driver. This is documented at [[No-Slot_Clock#WDC_CPUs]].		The WDC 65C16S has a timing incompatibility with the [[No-Slot Clock]] and must use a modified driver. This is documented at [[No-Slot_Clock#WDC_CPUs]].

			=== ADTPro ===
			ADTPro-2.1.0 attempts to unilaterally disable the ZipChip and TransWarp accelerators during a critical timing loop. Unfortunately, that causes the UltraWarp to corrupt the screen.

			Replacing the offending instructions with instructions appropriate for the UltraWarp solves the problem.

			A zipfile containing the patched ADTPro client is at the bottom of this page.

	== Controlling Speed ==		== Controlling Speed ==
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	<gallery class="center" widths=150px heights=80 caption="2017 Edition">		<gallery class="center" widths=150px heights=80 caption="2017 Edition">
	File:PDF_ICON.svg\|UltraWarp Manual\|link=http://wiki.reactivemicro.com/images/1/13/UltraWarp_v1.91G_-_Users_Guide.pdf		File:PDF_ICON.svg\|UltraWarp Manual\|link=http://wiki.reactivemicro.com/images/1/13/UltraWarp_v1.91G_-_Users_Guide.pdf

			File:5.25floppy.jpg\|ADTPro-2.1.0uw\|link=https://wiki.reactivemicro.com/images/f/fc/ADTPro-2.1.0uw.zip
	</gallery>		</gallery>
	</div>		</div>

Cryu: Move DIP switch to own section

2023-10-04T04:06:17Z

Move DIP switch to own section

← Older revision		Revision as of 21:06, 3 October 2023
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	Note that you must warm-reset the machine with <code>control-reset</code> after disabling the UltraWarp (it will be automatically enabled at the next powerup). There is no need to reset the machine after the SLOW-POKE or FAST-POKE.		Note that you must warm-reset the machine with <code>control-reset</code> after disabling the UltraWarp (it will be automatically enabled at the next powerup). There is no need to reset the machine after the SLOW-POKE or FAST-POKE.

	DIP Switch Settings~~. All defaulted OFF. See the manual for details.~~		== DIP Switch Settings==
			By default, all switches are off
	*SW1 = Nothing (not connected/unused).		*SW1 = Nothing (not connected/unused).
	*SW2 = Joystick Delay. When set ON accesses to $C070 cause a 2.5 millisecond delay.		*SW2 = Joystick Delay. When set ON accesses to $C070 cause a 2.5 millisecond delay.

Cryu: Fix typo

2023-10-04T03:57:43Z

Fix typo

← Older revision		Revision as of 20:57, 3 October 2023
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	! Location !! Function		! Location !! Function
	\|-		\|-
	\| $~~C05D~~ \|\| ~~Low speed (1 MHz)~~		\| $C05B \|\| Disable
	\|-		\|-
	\| $C05C \|\| High speed (set on power-up)		\| $C05C \|\| High speed (set on power-up)
	\|-		\|-
	\| $~~C05B~~ \|\| ~~Disable~~		\| $C05D \|\| Low speed (1 MHz)
	\|}		\|}

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	This disables the UltraWarp:		This disables the UltraWarp:

	<code>POKE ~~49245~~,0</code>		<code>POKE 49243,0</code>

	Note that you must warm-reset the machine with <code>control-reset</code> after disabling the UltraWarp (it will be automatically enabled at the next powerup). There is no need to reset the machine after the SLOW-POKE or FAST-POKE.		Note that you must warm-reset the machine with <code>control-reset</code> after disabling the UltraWarp (it will be automatically enabled at the next powerup). There is no need to reset the machine after the SLOW-POKE or FAST-POKE.

Cryu: Misc fixes (formatting, dead link)

2023-10-04T03:54:58Z

Misc fixes (formatting, dead link)

← Older revision		Revision as of 20:54, 3 October 2023
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	** Avoiding the first few pages of RamWorks banks 0 and 1 may dodge this issue, but it's not clear why that would be the case.		** Avoiding the first few pages of RamWorks banks 0 and 1 may dodge this issue, but it's not clear why that would be the case.

	Michael Mengel had some feedback about this issue as well. He stated:~~<br>~~		Michael Mengel had some feedback about this issue as well. He stated:
	During the startup or load sequence the RAMWORKS size should be detected correctly. Detecting the ram size “in between” or from BASIC requires a mod. The apple ][ RAM test Utility v1.4 from the website www.ivanhogan.com contains the BASIC program RW.AUX.TEST. By adding the line:<br>
	~~191 POKE 49384,0 : REM Motor off<br>~~
	~~the correct RAMWORKS ram size should be displayed.<br>~~

	The ~~AE Super Desktop Expander~~ Utility ~~Disk~~ contains the BASIC program ~~STARTUP~~.~~BAS by Michael Wilks~~. ~~The mod here:~~<br>		<blockquote>
	~~188 POKE 49384,0<br>~~		During the startup or load sequence the RAMWORKS size should be detected correctly. Detecting the ram size “in between” or from BASIC requires a mod. The apple ][ RAM test Utility v1.4 from the website [http://www.ivanhogan.com/kfest/MemUtil/ www.ivanhogan.com]contains the BASIC program <code>RW.AUX.TEST</code>. By adding the line:
	~~to display~~ the ~~correct RAMWORKS ram size.<br>~~
	~~[END]~~

			<code>191 POKE 49384,0 : REM Motor off</code>

			the correct RAMWORKS ram size should be displayed.
			</blockquote>

			Similarly, the AE Super Desktop Expander Utility Disk contains the BASIC program STARTUP.BAS by Michael Wilks. Adding:

			<code>188 POKE 49384,0</code>

			results in the correct RAM size being displayed.

	=== No-Slot Clock ===		=== No-Slot Clock ===

Cryu: Streamline a bit with WikiCode

2023-10-04T03:47:09Z

Streamline a bit with WikiCode

← Older revision		Revision as of 20:47, 3 October 2023
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	== Controlling Speed ==		== Controlling Speed ==
	Like all accelerators for the Apple II, the UltraWarp can also be controlled by softswitches. There is also a ~~Dip Switch~~ which can control the ~~slot speeds~~.		Like all accelerators for the Apple II, the UltraWarp can also be controlled by softswitches. There is also a DIP switch which can control the access speed for slots 5 and 7.

	Location~~:<br>~~		{\| class="wikitable" style="margin:auto"
	$C05D ~~  -  ~~ Low speed (1 MHz)~~<br>~~		\|+ Soft Switches
	$C05C ~~  -  ~~ High speed (set on power-up)		\|-
	$C05B ~~  -  ~~ Disable		! Location !! Function
			\|-
			\| $C05D \|\| Low speed (1 MHz)
			\|-
			\| $C05C \|\| High speed (set on power-up)
			\|-
			\| $C05B \|\| Disable
			\|}

	The following example in Applesoft Basic will slow the UW to the 1 MHz clock rate: ~~POKE 49245,0<br>~~		The following example in Applesoft Basic will slow the UltraWarp to the 1 MHz clock rate:
	~~Next example switches back to full speed: POKE 49244,0<br>~~

	There is NO need ~~for RESET~~ after the SLOW-POKE or FAST-POKE.		<code>POKE 49245,0</code>

			The next example switches back to full speed:

			<code>POKE 49244,0</code>

			This disables the UltraWarp:

			<code>POKE 49245,0</code>

			Note that you must warm-reset the machine with <code>control-reset</code> after disabling the UltraWarp (it will be automatically enabled at the next powerup). There is no need to reset the machine after the SLOW-POKE or FAST-POKE.

	DIP Switch Settings. All defaulted OFF. See the manual for details.		DIP Switch Settings. All defaulted OFF. See the manual for details.
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	*SW3 = When set ON controls delay on Slot 5 to 1MHz.		*SW3 = When set ON controls delay on Slot 5 to 1MHz.
	*SW4 = When set ON controls delay on Slot 7 to 1MHz.		*SW4 = When set ON controls delay on Slot 7 to 1MHz.


	== Documentation ==		== Documentation ==

Cryu: Refer to No-Slot Clock documentation for compatibility

2023-10-04T03:37:37Z

Refer to No-Slot Clock documentation for compatibility

← Older revision		Revision as of 20:37, 3 October 2023
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	=== No-Slot Clock ===		=== No-Slot Clock ===
	~~There~~ has ~~been~~ a ~~reported issue~~ with the ~~UltraWarp and the~~ No-Slot Clock ~~when used together.~~		The WDC 65C16S has a timing incompatibility with the [[No-Slot Clock]] and must use a modified driver. This is documented at [[No-Slot_Clock#WDC_CPUs]].

	~~Bobbi Webber-Manners reported the following:<br>~~
	~~No Slot Clock works fine with the Ultrawarp disabled (ie: STA $C050B) using NS.CLOCK.SYSTEM~~ and ~~NSCUTIL.SYSTEM.<br>~~
	~~With the Ultrawarp enabled, at either 1MHz (ie: STA $C05D) mode or at the full 13MHz, NSCUTIL.SYSTEM still works file, but NS.CLOCK.SYSTEM is unable to read the No Slot Clock.<br>~~
	~~I played around with NS.CLOCK.SYSTEM to try to investigate the issue~~. ~~As you can see from the above, it~~ is ~~not an issue of the accelerator speed since it fails with UW~~ at ~~1MHz.<br>~~
	I discovered that inserting a load from somewhere in $C0xx in NS.CLOCK.SYSTEM magically made it work. I settled on LDA $C00B, since this seems to have no documented effects. I built a modified NS.CLOCK.SYSTEM called NS.CLKUW.SYSTEM which seems to work fine on all systems with or without UW installed. This seems to be a corner-~~case bug in the Ultrawarp logic~~.~~<br>~~
	~~Modded and fixed NS.CLKUW.SYSTEM can be found here: https://github.com/bobbimanners/ProDOS-Utils/tree/master/No_Slot_Clock<br>~~
	~~[END]~~

	== Controlling Speed ==		== Controlling Speed ==

RMHenry: /* Compatibility And Known Issues */

2023-06-29T23:09:46Z

Compatibility And Known Issues

← Older revision		Revision as of 16:09, 29 June 2023
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	\|}		\|}

	* = The designer of the UW has confirmed that replacing U40 and U41 with ~~74```LS```373~~ ICs fixes the BOOTI issue. TotalReplay 5.0 and A2Desktop will work correctly as well. ReActiveMicro is working on confirming this mod, and will update stock for new sales.		* = The designer of the UW has confirmed that replacing U40 and U41 with 74LS373 ICs fixes the BOOTI issue. TotalReplay 5.0 and A2Desktop will work correctly as well. ReActiveMicro is working on confirming this mod, and will update stock for new sales.

RMHenry: /* Compatibility And Known Issues */

2023-06-29T23:09:31Z

Compatibility And Known Issues

← Older revision		Revision as of 16:09, 29 June 2023
Line 243:		Line 243:
	\|}		\|}

	* = The designer of the UW has confirmed that replacing U40 and U41 with 74``LS``373 ICs fixes the BOOTI issue. TotalReplay 5.0 and A2Desktop will work correctly as well. ReActiveMicro is working on confirming this mod, and will update stock for new sales.		* = The designer of the UW has confirmed that replacing U40 and U41 with 74```LS```373 ICs fixes the BOOTI issue. TotalReplay 5.0 and A2Desktop will work correctly as well. ReActiveMicro is working on confirming this mod, and will update stock for new sales.