cpldfit:  version P.20131013                        Xilinx Inc.
                                  Fitter Report
Design Name: A2_SD_TOP                           Date: 11- 3-2018,  2:38PM
Device Used: XC9572XL-10-TQ100
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
24 /72  ( 33%) 26  /360  (  7%) 34 /216 ( 16%)   10 /72  ( 14%) 38 /72  ( 53%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1           8/18       11/54       15/90       8/18
FB2           9/18       14/54        2/90      13/18
FB3           3/18        4/54        6/90       4/18
FB4           4/18        5/54        3/90      13/18
             -----       -----       -----      -----    
             24/72       34/216      26/360     38/72 

* - Resource is exhausted

** Global Control Resources **

Signal 'clk_7m' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Signal 'n_reset' mapped onto global set/reset net GSR.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   17          17    |  I/O              :    33      66
Output        :   15          15    |  GCK/IO           :     2       3
Bidirectional :    4           4    |  GTS/IO           :     2       2
GCK           :    1           1    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    1           1    |
                 ----        ----
        Total     38          38

** Power Data **

There are 24 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'A2_SD_TOP.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'clk_7m' based upon the LOC
   constraint 'P22'. It is recommended that you declare this BUFG explicitedly
   in your design. Note that for certain device families the output of a BUFG
   constraint can not drive a gated clock, and the BUFG constraint will be
   ignored.
INFO:Cpld - Inferring BUFG constraint for signal 'clk_ph1' based upon the LOC
   constraint 'P23'. It is recommended that you declare this BUFG explicitedly
   in your design. Note that for certain device families the output of a BUFG
   constraint can not drive a gated clock, and the BUFG constraint will be
   ignored.
WARNING:Cpld:936 - The output buffer 'n_nmi_OBUF' is missing an input and will
   be deleted.
WARNING:Cpld:936 - The output buffer 'flash_addr<18>_OBUF' is missing an input
   and will be deleted.
WARNING:Cpld:936 - The output buffer 'flash_addr<17>_OBUF' is missing an input
   and will be deleted.
WARNING:Cpld:936 - The output buffer 'flash_addr<16>_OBUF' is missing an input
   and will be deleted.
WARNING:Cpld:936 - The output buffer 'flash_addr<15>_OBUF' is missing an input
   and will be deleted.
WARNING:Cpld:936 - The output buffer 'flash_addr<14>_OBUF' is missing an input
   and will be deleted.
WARNING:Cpld:936 - The output buffer 'flash_addr<13>_OBUF' is missing an input
   and will be deleted.
WARNING:Cpld:936 - The output buffer 'flash_addr<12>_OBUF' is missing an input
   and will be deleted.
WARNING:Cpld:936 - The output buffer 'addr_en_OBUF' is missing an input and will
   be deleted.
WARNING:Cpld:1007 - Removing unused input(s) 'clk_ph1'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'cpu_addr<11>'.  The input(s) are
   unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'cpu_addr<12>'.  The input(s) are
   unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'cpu_addr<13>'.  The input(s) are
   unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'cpu_addr<14>'.  The input(s) are
   unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'cpu_addr<15>'.  The input(s) are
   unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'sd_detect'.  The input(s) are
   unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'sd_wprot'.  The input(s) are
   unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'spi_miso<0>'.  The input(s) are
   unused after optimization. Please verify functionality via simulation.
*************************  Summary of Mapped Logic  ************************

** 19 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
n_irq               0     0     FB1_8   17   I/O     O       STD  FAST 
ROM_n_oe            1     2     FB1_10  28   I/O     O       STD  FAST 
ROM_n_ce            1     2     FB1_14  27   GCK/I/O O       STD  FAST 
ROM_n_we            1     2     FB1_15  29   I/O     O       STD  FAST 
cpu_data<4>         0     0     FB2_2   94   I/O     O       STD  FAST 
cpu_data<1>         0     0     FB2_3   91   I/O     I/O     STD  FAST 
cpu_data<3>         0     0     FB2_4   93   I/O     I/O     STD  FAST 
cpu_data<5>         0     0     FB2_5   95   I/O     O       STD  FAST 
cpu_data<6>         0     0     FB2_6   96   I/O     O       STD  FAST 
cpu_data<7>         0     0     FB2_8   97   I/O     O       STD  FAST 
data_en             1     3     FB2_17  12   I/O     O       STD  FAST 
cpu_data<2>         0     0     FB2_18  92   I/O     I/O     STD  FAST 
spi_n_sel<3>        2     2     FB3_2   32   I/O     O       STD  FAST RESET
spi_n_sel<2>        2     2     FB3_7   54   I/O     O       STD  FAST RESET
spi_n_sel<1>        2     2     FB3_14  55   I/O     O       STD  FAST RESET
spi_n_sel<0>        2     2     FB4_1   65   I/O     O       STD  FAST RESET
spi_sclk            0     0     FB4_2   67   I/O     O       STD  FAST 
spi_mosi            1     4     FB4_9   66   I/O     O       STD  FAST RESET
cpu_data<0>         0     0     FB4_17  90   I/O     I/O     STD  FAST 

** 5 Buried Nodes **

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
SPI6502B/clksrc     1     1     FB1_13  STD  RESET
SPI6502B/divcnt<0>  3     5     FB1_16  STD  RESET
SPI6502B/divcnt<2>  4     5     FB1_17  STD  RESET
SPI6502B/divcnt<1>  4     5     FB1_18  STD  RESET
EEPROM_n_OE/XLXN_5  1     12    FB2_16  STD  RESET

** 19 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
r_nw                FB1_5   14   I/O     I
n_iostrobe          FB1_6   15   I/O     I
clk_ph0             FB1_7   25   I/O     I
clk_7m              FB1_9   22   GCK/I/O GCK
cpu_addr<6>         FB2_1   87   I/O     I
cpu_addr<9>         FB2_7   3    GTS/I/O I
n_reset             FB2_9   99   GSR/I/O GSR/I
cpu_addr<8>         FB2_10  1    I/O     I
cpu_addr<10>        FB2_11  4    GTS/I/O I
jmp_we              FB3_9   42   I/O     I
n_iosel             FB4_6   76   I/O     I
n_devsel            FB4_7   77   I/O     I
cpu_addr<2>         FB4_10  81   I/O     I
cpu_addr<3>         FB4_12  82   I/O     I
cpu_addr<4>         FB4_13  85   I/O     I
cpu_addr<0>         FB4_14  78   I/O     I
cpu_addr<7>         FB4_15  89   I/O     I
cpu_addr<5>         FB4_16  86   I/O     I
cpu_addr<1>         FB4_18  79   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               11/43
Number of signals used by logic mapping into function block:  11
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1   16    I/O     
(unused)              0       0     0   5     FB1_2   13    I/O     
(unused)              0       0     0   5     FB1_3   18    I/O     
(unused)              0       0     0   5     FB1_4   20    I/O     
(unused)              0       0     0   5     FB1_5   14    I/O     I
(unused)              0       0     0   5     FB1_6   15    I/O     I
(unused)              0       0     0   5     FB1_7   25    I/O     I
n_irq                 0       0     0   5     FB1_8   17    I/O     O
(unused)              0       0     0   5     FB1_9   22    GCK/I/O GCK
ROM_n_oe              1       0     0   4     FB1_10  28    I/O     O
(unused)              0       0     0   5     FB1_11  23    GCK/I/O 
(unused)              0       0     0   5     FB1_12  33    I/O     
SPI6502B/clksrc       1       0     0   4     FB1_13  36    I/O     (b)
ROM_n_ce              1       0     0   4     FB1_14  27    GCK/I/O O
ROM_n_we              1       0     0   4     FB1_15  29    I/O     O
SPI6502B/divcnt<0>    3       0     0   2     FB1_16  39    I/O     (b)
SPI6502B/divcnt<2>    4       0     0   1     FB1_17  30    I/O     (b)
SPI6502B/divcnt<1>    4       0     0   1     FB1_18  40    I/O     (b)

Signals Used by Logic in Function Block
  1: EEPROM_n_OE/XLXN_5   5: SPI6502B/divcnt<2>   9: n_iostrobe 
  2: SPI6502B/clksrc      6: clk_ph0             10: n_reset 
  3: SPI6502B/divcnt<0>   7: jmp_we              11: r_nw 
  4: SPI6502B/divcnt<1>   8: n_iosel            

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
n_irq                ........................................ 0
ROM_n_oe             X.........X............................. 2
SPI6502B/clksrc      .....X.................................. 1
ROM_n_ce             .......XX............................... 2
ROM_n_we             ......X...X............................. 2
SPI6502B/divcnt<0>   .XXXX....X.............................. 5
SPI6502B/divcnt<2>   .XXXX....X.............................. 5
SPI6502B/divcnt<1>   .XXXX....X.............................. 5
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               14/40
Number of signals used by logic mapping into function block:  14
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1   87    I/O     I
cpu_data<4>           0       0     0   5     FB2_2   94    I/O     O
cpu_data<1>           0       0     0   5     FB2_3   91    I/O     I/O
cpu_data<3>           0       0     0   5     FB2_4   93    I/O     I/O
cpu_data<5>           0       0     0   5     FB2_5   95    I/O     O
cpu_data<6>           0       0     0   5     FB2_6   96    I/O     O
(unused)              0       0     0   5     FB2_7   3     GTS/I/O I
cpu_data<7>           0       0     0   5     FB2_8   97    I/O     O
(unused)              0       0     0   5     FB2_9   99    GSR/I/O GSR/I
(unused)              0       0     0   5     FB2_10  1     I/O     I
(unused)              0       0     0   5     FB2_11  4     GTS/I/O I
(unused)              0       0     0   5     FB2_12  6     I/O     
(unused)              0       0     0   5     FB2_13  8     I/O     
(unused)              0       0     0   5     FB2_14  9     I/O     
(unused)              0       0     0   5     FB2_15  11    I/O     
EEPROM_n_OE/XLXN_5    1       0     0   4     FB2_16  10    I/O     (b)
data_en               1       0     0   4     FB2_17  12    I/O     O
cpu_data<2>           0       0     0   5     FB2_18  92    I/O     I/O

Signals Used by Logic in Function Block
  1: cpu_addr<0>        6: cpu_addr<4>       11: cpu_addr<9> 
  2: cpu_addr<10>       7: cpu_addr<5>       12: n_devsel 
  3: cpu_addr<1>        8: cpu_addr<6>       13: n_iosel 
  4: cpu_addr<2>        9: cpu_addr<7>       14: n_iostrobe 
  5: cpu_addr<3>       10: cpu_addr<8>      

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
cpu_data<4>          ........................................ 0
cpu_data<1>          ........................................ 0
cpu_data<3>          ........................................ 0
cpu_data<5>          ........................................ 0
cpu_data<6>          ........................................ 0
cpu_data<7>          ........................................ 0
EEPROM_n_OE/XLXN_5   XXXXXXXXXXX..X.......................... 12
data_en              ...........XXX.......................... 3
cpu_data<2>          ........................................ 0
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               4/50
Number of signals used by logic mapping into function block:  4
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1   41    I/O     
spi_n_sel<3>          2       0     0   3     FB3_2   32    I/O     O
(unused)              0       0     0   5     FB3_3   49    I/O     
(unused)              0       0     0   5     FB3_4   50    I/O     
(unused)              0       0     0   5     FB3_5   35    I/O     
(unused)              0       0     0   5     FB3_6   53    I/O     
spi_n_sel<2>          2       0     0   3     FB3_7   54    I/O     O
(unused)              0       0     0   5     FB3_8   37    I/O     
(unused)              0       0     0   5     FB3_9   42    I/O     I
(unused)              0       0     0   5     FB3_10  60    I/O     
(unused)              0       0     0   5     FB3_11  52    I/O     
(unused)              0       0     0   5     FB3_12  61    I/O     
(unused)              0       0     0   5     FB3_13  63    I/O     
spi_n_sel<1>          2       0     0   3     FB3_14  55    I/O     O
(unused)              0       0     0   5     FB3_15  56    I/O     
(unused)              0       0     0   5     FB3_16  64    I/O     
(unused)              0       0     0   5     FB3_17  58    I/O     
(unused)              0       0     0   5     FB3_18  59    I/O     

Signals Used by Logic in Function Block
  1: cpu_data<2>.PIN    3: cpu_data<0>.PIN    4: SPI6502B/clksrc 
  2: cpu_data<1>.PIN  

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
spi_n_sel<3>         ..XX.................................... 2
spi_n_sel<2>         .X.X.................................... 2
spi_n_sel<1>         X..X.................................... 2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               5/49
Number of signals used by logic mapping into function block:  5
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
spi_n_sel<0>          2       0     0   3     FB4_1   65    I/O     O
spi_sclk              0       0     0   5     FB4_2   67    I/O     O
(unused)              0       0     0   5     FB4_3   71    I/O     
(unused)              0       0     0   5     FB4_4   72    I/O     
(unused)              0       0     0   5     FB4_5   68    I/O     
(unused)              0       0     0   5     FB4_6   76    I/O     I
(unused)              0       0     0   5     FB4_7   77    I/O     I
(unused)              0       0     0   5     FB4_8   70    I/O     
spi_mosi              1       0     0   4     FB4_9   66    I/O     O
(unused)              0       0     0   5     FB4_10  81    I/O     I
(unused)              0       0     0   5     FB4_11  74    I/O     
(unused)              0       0     0   5     FB4_12  82    I/O     I
(unused)              0       0     0   5     FB4_13  85    I/O     I
(unused)              0       0     0   5     FB4_14  78    I/O     I
(unused)              0       0     0   5     FB4_15  89    I/O     I
(unused)              0       0     0   5     FB4_16  86    I/O     I
cpu_data<0>           0       0     0   5     FB4_17  90    I/O     I/O
(unused)              0       0     0   5     FB4_18  79    I/O     I

Signals Used by Logic in Function Block
  1: cpu_data<3>.PIN    3: SPI6502B/divcnt<0>   5: SPI6502B/divcnt<2> 
  2: SPI6502B/clksrc    4: SPI6502B/divcnt<1> 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
spi_n_sel<0>         XX...................................... 2
spi_sclk             ........................................ 0
spi_mosi             .XXXX................................... 4
cpu_data<0>          ........................................ 0
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********

FDCPE_EEPROM_n_OE/XLXN_5: FDCPE port map (EEPROM_n_OE/XLXN_5,EEPROM_n_OE/XLXN_5_D,'1','0','0');
EEPROM_n_OE/XLXN_5_D <= (cpu_addr(7) AND cpu_addr(6) AND cpu_addr(5) AND 
	cpu_addr(4) AND cpu_addr(3) AND cpu_addr(2) AND cpu_addr(1) AND 
	cpu_addr(0) AND NOT n_iostrobe AND cpu_addr(9) AND cpu_addr(8) AND 
	cpu_addr(10));


ROM_n_ce <= (n_iostrobe AND n_iosel);


ROM_n_oe <= NOT ((r_nw AND EEPROM_n_OE/XLXN_5));


ROM_n_we <= NOT ((NOT r_nw AND jmp_we));

FDCPE_SPI6502B/clksrc: FDCPE port map (SPI6502B/clksrc,NOT clk_ph0,clk_7m,'0','0');

FTCPE_SPI6502B/divcnt0: FTCPE port map (SPI6502B/divcnt(0),SPI6502B/divcnt_T(0),NOT SPI6502B/clksrc,NOT n_reset,'0');
SPI6502B/divcnt_T(0) <= ((NOT n_reset AND NOT SPI6502B/divcnt(0))
	OR (NOT SPI6502B/divcnt(0) AND NOT SPI6502B/divcnt(1) AND 
	NOT SPI6502B/divcnt(2) AND SPI6502B/clksrc));

FDCPE_SPI6502B/divcnt1: FDCPE port map (SPI6502B/divcnt(1),SPI6502B/divcnt_D(1),NOT SPI6502B/clksrc,NOT n_reset,'0');
SPI6502B/divcnt_D(1) <= ((n_reset AND SPI6502B/divcnt(0) AND 
	SPI6502B/divcnt(1))
	OR (n_reset AND NOT SPI6502B/divcnt(0) AND 
	NOT SPI6502B/divcnt(1) AND SPI6502B/divcnt(2))
	OR (n_reset AND NOT SPI6502B/divcnt(0) AND 
	NOT SPI6502B/divcnt(1) AND NOT SPI6502B/clksrc));

FDCPE_SPI6502B/divcnt2: FDCPE port map (SPI6502B/divcnt(2),SPI6502B/divcnt_D(2),NOT SPI6502B/clksrc,NOT n_reset,'0');
SPI6502B/divcnt_D(2) <= ((n_reset AND SPI6502B/divcnt(0) AND 
	SPI6502B/divcnt(2))
	OR (n_reset AND SPI6502B/divcnt(1) AND 
	SPI6502B/divcnt(2))
	OR (n_reset AND NOT SPI6502B/divcnt(0) AND 
	NOT SPI6502B/divcnt(1) AND NOT SPI6502B/divcnt(2) AND NOT SPI6502B/clksrc));


cpu_data_I(0) <= '0';
cpu_data(0) <= cpu_data_I(0) when cpu_data_OE(0) = '1' else 'Z';
cpu_data_OE(0) <= '0';


cpu_data_I(1) <= '0';
cpu_data(1) <= cpu_data_I(1) when cpu_data_OE(1) = '1' else 'Z';
cpu_data_OE(1) <= '0';


cpu_data_I(2) <= '0';
cpu_data(2) <= cpu_data_I(2) when cpu_data_OE(2) = '1' else 'Z';
cpu_data_OE(2) <= '0';


cpu_data_I(3) <= '0';
cpu_data(3) <= cpu_data_I(3) when cpu_data_OE(3) = '1' else 'Z';
cpu_data_OE(3) <= '0';


cpu_data_I(4) <= '0';
cpu_data(4) <= cpu_data_I(4) when cpu_data_OE(4) = '1' else 'Z';
cpu_data_OE(4) <= '0';


cpu_data_I(5) <= '0';
cpu_data(5) <= cpu_data_I(5) when cpu_data_OE(5) = '1' else 'Z';
cpu_data_OE(5) <= '0';


cpu_data_I(6) <= '0';
cpu_data(6) <= cpu_data_I(6) when cpu_data_OE(6) = '1' else 'Z';
cpu_data_OE(6) <= '0';


cpu_data_I(7) <= '0';
cpu_data(7) <= cpu_data_I(7) when cpu_data_OE(7) = '1' else 'Z';
cpu_data_OE(7) <= '0';


data_en <= (n_iostrobe AND n_iosel AND n_devsel);


n_irq_I <= '0';
n_irq <= n_irq_I when n_irq_OE = '1' else 'Z';
n_irq_OE <= '0';

FDCPE_spi_mosi: FDCPE port map (spi_mosi,'1',spi_mosi_C,'0',NOT n_reset);
spi_mosi_C <= (NOT SPI6502B/divcnt(0) AND NOT SPI6502B/divcnt(1) AND 
	NOT SPI6502B/divcnt(2) AND SPI6502B/clksrc);

FDCPE_spi_n_sel0: FDCPE port map (spi_n_sel(0),cpu_data(3).PIN,NOT SPI6502B/clksrc,'0',NOT n_reset,'0');

FDCPE_spi_n_sel1: FDCPE port map (spi_n_sel(1),cpu_data(2).PIN,NOT SPI6502B/clksrc,'0',NOT n_reset,'0');

FDCPE_spi_n_sel2: FDCPE port map (spi_n_sel(2),cpu_data(1).PIN,NOT SPI6502B/clksrc,'0',NOT n_reset,'0');

FDCPE_spi_n_sel3: FDCPE port map (spi_n_sel(3),cpu_data(0).PIN,NOT SPI6502B/clksrc,'0',NOT n_reset,'0');


spi_sclk <= '0';

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572XL-10-TQ100


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  /100 98  96  94  92  90  88  86  84  82  80  78  76  \
 |   99  97  95  93  91  89  87  85  83  81  79  77    |
 | 1                                               75  | 
 | 2                                               74  | 
 | 3                                               73  | 
 | 4                                               72  | 
 | 5                                               71  | 
 | 6                                               70  | 
 | 7                                               69  | 
 | 8                                               68  | 
 | 9                                               67  | 
 | 10                                              66  | 
 | 11                                              65  | 
 | 12                                              64  | 
 | 13               XC9572XL-10-TQ100              63  | 
 | 14                                              62  | 
 | 15                                              61  | 
 | 16                                              60  | 
 | 17                                              59  | 
 | 18                                              58  | 
 | 19                                              57  | 
 | 20                                              56  | 
 | 21                                              55  | 
 | 22                                              54  | 
 | 23                                              53  | 
 | 24                                              52  | 
 | 25                                              51  | 
 |   27  29  31  33  35  37  39  41  43  45  47  49    |
  \26  28  30  32  34  36  38  40  42  44  46  48  50  /
   --------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 cpu_addr<8>                      51 VCC                           
  2 NC                               52 KPR                           
  3 cpu_addr<9>                      53 KPR                           
  4 cpu_addr<10>                     54 spi_n_sel<2>                  
  5 VCC                              55 spi_n_sel<1>                  
  6 KPR                              56 KPR                           
  7 NC                               57 VCC                           
  8 KPR                              58 KPR                           
  9 KPR                              59 KPR                           
 10 KPR                              60 KPR                           
 11 KPR                              61 KPR                           
 12 data_en                          62 GND                           
 13 KPR                              63 KPR                           
 14 r_nw                             64 KPR                           
 15 n_iostrobe                       65 spi_n_sel<0>                  
 16 KPR                              66 spi_mosi                      
 17 n_irq                            67 spi_sclk                      
 18 KPR                              68 KPR                           
 19 NC                               69 GND                           
 20 KPR                              70 KPR                           
 21 GND                              71 KPR                           
 22 clk_7m                           72 KPR                           
 23 KPR                              73 NC                            
 24 NC                               74 KPR                           
 25 clk_ph0                          75 GND                           
 26 VCC                              76 n_iosel                       
 27 ROM_n_ce                         77 n_devsel                      
 28 ROM_n_oe                         78 cpu_addr<0>                   
 29 ROM_n_we                         79 cpu_addr<1>                   
 30 KPR                              80 NC                            
 31 GND                              81 cpu_addr<2>                   
 32 spi_n_sel<3>                     82 cpu_addr<3>                   
 33 KPR                              83 TDO                           
 34 NC                               84 GND                           
 35 KPR                              85 cpu_addr<4>                   
 36 KPR                              86 cpu_addr<5>                   
 37 KPR                              87 cpu_addr<6>                   
 38 VCC                              88 VCC                           
 39 KPR                              89 cpu_addr<7>                   
 40 KPR                              90 cpu_data<0>                   
 41 KPR                              91 cpu_data<1>                   
 42 jmp_we                           92 cpu_data<2>                   
 43 NC                               93 cpu_data<3>                   
 44 GND                              94 cpu_data<4>                   
 45 TDI                              95 cpu_data<5>                   
 46 NC                               96 cpu_data<6>                   
 47 TMS                              97 cpu_data<7>                   
 48 TCK                              98 VCC                           
 49 KPR                              99 n_reset                       
 50 KPR                             100 GND                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-10-TQ100
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25