A2_SD_TOP Project Status (11/03/2018 - 14:39:00) | |||
Project File: | A2_SD.xise | Parser Errors: | No Errors |
Module Name: | A2_SD_TOP | Implementation State: | Fitted |
Target Device: | xc9572xl-10TQ100 |
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No Errors |
Product Version: | ISE 14.7 |
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94 Warnings (3 new, 0 filtered) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sat Nov 3 14:37:15 2018 | 0 | 94 Warnings (3 new, 0 filtered) | 3 Infos (0 new, 0 filtered) | |
Translation Report | Current | Sat Nov 3 14:38:40 2018 | 0 | 0 | 0 | |
CPLD Fitter Report (Text) | Current | Sat Nov 3 14:38:46 2018 | 0 | 19 Warnings (1 new, 0 filtered) | 2 Infos (2 new, 0 filtered) | |
Power Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
Post-Fit Simulation Model Report |