Timing Report

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Design Name A2_SD_TOP
Device, Speed (SpeedFile Version) XC9572XL, -10 (3.0)
Date Created Sat Nov 03 14:38:55 2018
Created By Timing Report Generator: version P.20131013
Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'spi_mosi.CLKF' has multiple original clock nets 'SPI6502B/divcnt<2>.Q' 'SPI6502B/divcnt<1>.Q' 'SPI6502B/divcnt<0>.Q' 'SPI6502B/clksrc.Q'.

Performance Summary
Min. Clock Period 14.000 ns.
Max. Clock Frequency (fSYSTEM) 71.429 MHz.
Limited by Clock Pulse Width for SPI6502B/divcnt<2>.Q
Clock to Setup (tCYC) 10.000 ns.
Pad to Pad Delay (tPD) 10.000 ns.
Setup to Clock at the Pad (tSU) 6.500 ns.
Clock Pad to Output Pad Delay (tCO) 21.600 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
TS1004 0.0 0.0 0 0
TS1005 0.0 0.0 0 0
AUTO_TS_F2F 0.0 10.0 12 12
AUTO_TS_P2P 0.0 21.6 13 13
AUTO_TS_P2F 0.0 8.3 21 21
AUTO_TS_F2P 0.0 4.0 5 5


Constraint: TS1000

Description: PERIOD:PERIOD_EEPROM_n_OE/XLXN_5.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_SPI6502B/divcnt<2>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_SPI6502B/divcnt<1>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_SPI6502B/divcnt<0>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1004

Description: PERIOD:PERIOD_clk_7m:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1005

Description: PERIOD:PERIOD_SPI6502B/clksrc.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
SPI6502B/clksrc.Q to SPI6502B/divcnt<0>.D 0.000 10.000 -10.000
SPI6502B/clksrc.Q to SPI6502B/divcnt<1>.D 0.000 10.000 -10.000
SPI6502B/clksrc.Q to SPI6502B/divcnt<2>.D 0.000 10.000 -10.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
clk_7m to spi_mosi 0.000 21.600 -21.600
clk_7m to spi_n_sel<0> 0.000 13.700 -13.700
clk_7m to spi_n_sel<1> 0.000 13.700 -13.700


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
clk_ph0 to SPI6502B/clksrc.D 0.000 8.300 -8.300
cpu_addr<0> to EEPROM_n_OE/XLXN_5.D 0.000 8.300 -8.300
cpu_addr<10> to EEPROM_n_OE/XLXN_5.D 0.000 8.300 -8.300


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
spi_mosi.Q to spi_mosi 0.000 4.000 -4.000
spi_n_sel<0>.Q to spi_n_sel<0> 0.000 4.000 -4.000
spi_n_sel<1>.Q to spi_n_sel<1> 0.000 4.000 -4.000



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
SPI6502B/divcnt<2>.Q 71.429 Limited by Clock Pulse Width for SPI6502B/divcnt<2>.Q
SPI6502B/divcnt<1>.Q 71.429 Limited by Clock Pulse Width for SPI6502B/divcnt<1>.Q
SPI6502B/divcnt<0>.Q 71.429 Limited by Clock Pulse Width for SPI6502B/divcnt<0>.Q
clk_7m 111.111 Limited by Clock Pulse Width for clk_7m
SPI6502B/clksrc.Q 71.429 Limited by Clock Pulse Width for SPI6502B/clksrc.Q

Setup/Hold Times for Clocks

Setup/Hold Times for Clock EEPROM_n_OE/XLXN_5.CLKF
Source Pad Setup to clk (edge) Hold to clk (edge)

Setup/Hold Times for Clock clk_7m
Source Pad Setup to clk (edge) Hold to clk (edge)
clk_ph0 6.500 0.000

Setup/Hold Times for Clock SPI6502B/clksrc.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
cpu_data<0> 0.400 3.100
cpu_data<1> 0.400 3.100
cpu_data<2> 0.400 3.100
cpu_data<3> 0.400 3.100
n_reset 0.400 3.100


Clock to Pad Timing

Clock clk_7m to Pad
Destination Pad Clock (edge) to Pad
spi_mosi 21.600
spi_n_sel<0> 13.700
spi_n_sel<1> 13.700
spi_n_sel<2> 13.700
spi_n_sel<3> 13.700


Clock to Setup Times for Clocks

Clock to Setup for clock SPI6502B/clksrc.Q
Source Destination Delay
SPI6502B/divcnt<0>.Q SPI6502B/divcnt<0>.D 10.000
SPI6502B/divcnt<0>.Q SPI6502B/divcnt<1>.D 10.000
SPI6502B/divcnt<0>.Q SPI6502B/divcnt<2>.D 10.000
SPI6502B/divcnt<1>.Q SPI6502B/divcnt<0>.D 10.000
SPI6502B/divcnt<1>.Q SPI6502B/divcnt<1>.D 10.000
SPI6502B/divcnt<1>.Q SPI6502B/divcnt<2>.D 10.000
SPI6502B/divcnt<2>.Q SPI6502B/divcnt<0>.D 10.000
SPI6502B/divcnt<2>.Q SPI6502B/divcnt<1>.D 10.000
SPI6502B/divcnt<2>.Q SPI6502B/divcnt<2>.D 10.000


Pad to Pad List

Source Pad Destination Pad Delay
jmp_we ROM_n_we 10.000
n_devsel data_en 10.000
n_iosel ROM_n_ce 10.000
n_iosel data_en 10.000
n_iostrobe ROM_n_ce 10.000
n_iostrobe data_en 10.000
r_nw ROM_n_oe 10.000
r_nw ROM_n_we 10.000



Number of paths analyzed: 51
Number of Timing errors: 51
Analysis Completed: Sat Nov 03 14:38:55 2018