A2_SD_TOP Project Status (11/03/2018 - 14:39:00)
Project File: A2_SD.xise Parser Errors: No Errors
Module Name: A2_SD_TOP Implementation State: Fitted
Target Device: xc9572xl-10TQ100
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
94 Warnings (3 new, 0 filtered)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat Nov 3 14:37:15 2018094 Warnings (3 new, 0 filtered)3 Infos (0 new, 0 filtered)
Translation ReportCurrentSat Nov 3 14:38:40 2018000
CPLD Fitter Report (Text)CurrentSat Nov 3 14:38:46 2018019 Warnings (1 new, 0 filtered)2 Infos (2 new, 0 filtered)
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Fit Simulation Model Report  

Date Generated: 11/03/2018 - 14:39:00