Equations

********** Mapped Logic **********
FDCPE_EEPROM_n_OE/XLXN_5: FDCPE port map (EEPROM_n_OE/XLXN_5,EEPROM_n_OE/XLXN_5_D,'1','0','0');
     EEPROM_n_OE/XLXN_5_D <= (cpu_addr(7) AND cpu_addr(6) AND cpu_addr(5) AND
      cpu_addr(4) AND cpu_addr(3) AND cpu_addr(2) AND cpu_addr(1) AND
      cpu_addr(0) AND NOT n_iostrobe AND cpu_addr(9) AND cpu_addr(8) AND
      cpu_addr(10));
ROM_n_ce <= (n_iostrobe AND n_iosel);
ROM_n_oe <= NOT ((r_nw AND EEPROM_n_OE/XLXN_5));
ROM_n_we <= NOT ((NOT r_nw AND jmp_we));
FDCPE_SPI6502B/clksrc: FDCPE port map (SPI6502B/clksrc,NOT clk_ph0,clk_7m,'0','0');
FTCPE_SPI6502B/divcnt0: FTCPE port map (SPI6502B/divcnt(0),SPI6502B/divcnt_T(0),NOT SPI6502B/clksrc,NOT n_reset,'0');
     SPI6502B/divcnt_T(0) <= ((NOT n_reset AND NOT SPI6502B/divcnt(0))
      OR (NOT SPI6502B/divcnt(0) AND NOT SPI6502B/divcnt(1) AND
      NOT SPI6502B/divcnt(2) AND SPI6502B/clksrc));
FDCPE_SPI6502B/divcnt1: FDCPE port map (SPI6502B/divcnt(1),SPI6502B/divcnt_D(1),NOT SPI6502B/clksrc,NOT n_reset,'0');
     SPI6502B/divcnt_D(1) <= ((n_reset AND SPI6502B/divcnt(0) AND
      SPI6502B/divcnt(1))
      OR (n_reset AND NOT SPI6502B/divcnt(0) AND
      NOT SPI6502B/divcnt(1) AND SPI6502B/divcnt(2))
      OR (n_reset AND NOT SPI6502B/divcnt(0) AND
      NOT SPI6502B/divcnt(1) AND NOT SPI6502B/clksrc));
FDCPE_SPI6502B/divcnt2: FDCPE port map (SPI6502B/divcnt(2),SPI6502B/divcnt_D(2),NOT SPI6502B/clksrc,NOT n_reset,'0');
     SPI6502B/divcnt_D(2) <= ((n_reset AND SPI6502B/divcnt(0) AND
      SPI6502B/divcnt(2))
      OR (n_reset AND SPI6502B/divcnt(1) AND
      SPI6502B/divcnt(2))
      OR (n_reset AND NOT SPI6502B/divcnt(0) AND
      NOT SPI6502B/divcnt(1) AND NOT SPI6502B/divcnt(2) AND NOT SPI6502B/clksrc));
cpu_data_I(0) <= '0';
     cpu_data(0) <= cpu_data_I(0) when cpu_data_OE(0) = '1' else 'Z';
     cpu_data_OE(0) <= '0';
cpu_data_I(1) <= '0';
     cpu_data(1) <= cpu_data_I(1) when cpu_data_OE(1) = '1' else 'Z';
     cpu_data_OE(1) <= '0';
cpu_data_I(2) <= '0';
     cpu_data(2) <= cpu_data_I(2) when cpu_data_OE(2) = '1' else 'Z';
     cpu_data_OE(2) <= '0';
cpu_data_I(3) <= '0';
     cpu_data(3) <= cpu_data_I(3) when cpu_data_OE(3) = '1' else 'Z';
     cpu_data_OE(3) <= '0';
cpu_data_I(4) <= '0';
     cpu_data(4) <= cpu_data_I(4) when cpu_data_OE(4) = '1' else 'Z';
     cpu_data_OE(4) <= '0';
cpu_data_I(5) <= '0';
     cpu_data(5) <= cpu_data_I(5) when cpu_data_OE(5) = '1' else 'Z';
     cpu_data_OE(5) <= '0';
cpu_data_I(6) <= '0';
     cpu_data(6) <= cpu_data_I(6) when cpu_data_OE(6) = '1' else 'Z';
     cpu_data_OE(6) <= '0';
cpu_data_I(7) <= '0';
     cpu_data(7) <= cpu_data_I(7) when cpu_data_OE(7) = '1' else 'Z';
     cpu_data_OE(7) <= '0';
data_en <= (n_iostrobe AND n_iosel AND n_devsel);
n_irq_I <= '0';
     n_irq <= n_irq_I when n_irq_OE = '1' else 'Z';
     n_irq_OE <= '0';
FDCPE_spi_mosi: FDCPE port map (spi_mosi,'1',spi_mosi_C,'0',NOT n_reset);
     spi_mosi_C <= (NOT SPI6502B/divcnt(0) AND NOT SPI6502B/divcnt(1) AND
      NOT SPI6502B/divcnt(2) AND SPI6502B/clksrc);
FDCPE_spi_n_sel0: FDCPE port map (spi_n_sel(0),cpu_data(3).PIN,NOT SPI6502B/clksrc,'0',NOT n_reset,'0');
FDCPE_spi_n_sel1: FDCPE port map (spi_n_sel(1),cpu_data(2).PIN,NOT SPI6502B/clksrc,'0',NOT n_reset,'0');
FDCPE_spi_n_sel2: FDCPE port map (spi_n_sel(2),cpu_data(1).PIN,NOT SPI6502B/clksrc,'0',NOT n_reset,'0');
FDCPE_spi_n_sel3: FDCPE port map (spi_n_sel(3),cpu_data(0).PIN,NOT SPI6502B/clksrc,'0',NOT n_reset,'0');
spi_sclk <= '0';
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);